Error Correction Coding for the WA4DSY 56KB RF modem
I'm offering a free copy of an experimental Error Correction Coded (ECC)
EPROM for the WA4DSY / PacComm 56KB RF modem. This may benefit users
who suffer from 60Hz line noise, radar pulse noise or just plain weak signals.
Click here to view a block diagram of the encoder.
What it does
Data errors caused by impulse noise will be
corrected before being sent to the user interface.
This should greatly increase the reliability on links
with impulse noise such as radar and 60HZ line noise.
Noise pulses 40 db stronger than the signal will not
cause errors if they are of short duration.
Pulse rates up to 800 pps can be tolerated.
Weak signal performance is improved about 3 DB.
For example, I set up two modems connected to each other
through 1 db step attenuators. I turned on ECC mode and
reduced the signal level until my ping test of 100 packets
of 1300 bytes showed a 1% loss. I then switched to
normal 56K mode. No packets were properly decoded. I took
out 3 db of attenuation to achieve a 3% packet loss. See the
scope photos below.
I had good results running ECC on the air through the 56KB full duplex bit regenerator.
During cold dry weather defective hardware on a power pole near the repeater site
causes considerable line noise. During these periods a user 30 miles distant could
only get about 20% of his packets through without ECC. When ECC was switched on
the success rate jumped to better than 85%.
There are limited resources in the Xilinx FPGA chip. I had
to remove some little used functions to make room for the
ECC functions. The ECC version can't respond to a remote
control signal and it can't be used as a stand-alone bit repeater.
However, it can still send a remote control signal and the ECC
signal will pass through a standard non-ECC 56KB bit repeater.
The ECC uses a rate 2/3 code. This means the users data
rate is 2/3 the modems bit rate because there is one parity
bit transmitted for every 2 data bits. The maximum through-put is 37.3KB.
The DCD (Data Carrier Detect) response time is much slower than the non-ECC version.
It can take as long as 8 MS from TX keyed to valid data. I suggest
setting your TXDELAY parameter to 16 ms or more if you are going through
a full duplex bit repeater.
The DCD signal will go true before valid data is
available at the user interface. This is the opposite of a squelch tail which
has always existed in WA4DSY modems. This "squelch header" hasn't caused
any problems for my Ottawa PI-2 cards.
The modems receiver clock output is not a square wave. It looks
like a 56khz clock with every 3rd pulse missing. In fact, this is
exactly how it is generated. This is a side effect of the 2/3 bit rate
reduction and the suppresson of the parity bits on the user interface.
If anyone has a problem with this please drop me an email.
Valid data is always present on the rising edge.
Modems with the original EPROM can't communicate with the ECC version.
Original 56KB and ECC modems can coexist on the same frequency
because the carrier detect (DCD) works the same in both models. Since
they recognize the presence each others signal, collisions can be avoided
even if data can't be exchanged.
The frequency memories in this EPROM are the same as the
production 56KROM04.BIN which is currently shipped with the modem.
Memory TX Freq RX Freq RC Code Tuneup Freq
______ _______ _______ _______ ___________
0 29.050 29.050 20 29.050
1 29.950 29.950 20 29.950
2 28.400 29.850 20 29.850
3 29.850 28.400 20 28.400
4 28.550 29.550 20 29.550
5 29.550 28.550 20 28.550
6 28.000 28.000 20 28.000
7 30.000 30.000 20 30.000
The ECC version can operate in both plain 56k and ECC modes by setting
DIP switch S4-3 to the desired mode. This switch is labled "repeater ON".
Since there isn't a repeater function in the EPROM I used that switch to
change modes. When S4-3 = OFF the modem is in normal 56KB mode.
When ON it's in ECC mode. I've also connected the mode select to
uninstalled front panel switch S5. A DigiKey part number EG1102-ND
switch can be installed if desired. AN EG1192-ND cap will also be required.
You also need to drill a hole in the front panel.
NOTE: This is an experimental EPROM. This is the first attempt
at doing ECC. The next version, if any, may not be backwards compatible.
Click here to download 56KEC04A.Zip , the EPROM image. (23K)
Unzip the file and program 56KEC04A.BIN into a 27C256 150ns or faster EPROM and
replace the original. Dip switch S4-3 must be ON to enable the ECC mode.
This EPROM code is Copyright 1996 by Dale Alan Heatherington
Results of sending 100 packets of length 1300 bytes with and without ECC
0DB relative signal level
Eye pattern observed for 3% packet loss
without error correction coding
-3DB relative signal level
Eye pattern observed for 1% packet loss
with error correction coding.
This is 3DB less signal than the first.
100% packet loss occurs at this signal
level without error correction coding.